Core processor and clock ceiling
The AM3352BZCZ60 is a Texas Instruments Sitara-series microprocessor built around a single ARM Cortex-A8 core, 32-bit bus width, clocked at 600 MHz. This is the maximum operating frequency; the actual throughput depends on the flash wait-state configuration and the memory controller's page policy. A NEON SIMD coprocessor handles single-instruction multiple-data operations — useful for signal processing or pixel manipulation without loading the main core. The part also includes a graphics acceleration block and separate controllers for LCD and touchscreen interfaces.
Memory interface and I/O voltage rails
The integrated RAM controller supports LPDDR, DDR2, DDR3, and DDR3L — a single BOM can span different memory technologies by adjusting the VREF and termination. The I/O voltage rails are 1.8 V and 3.3 V, which cover the common JEDEC standards for DDR and peripheral logic. Two USB 2.0 ports with integrated PHY eliminate the need for an external transceiver for host or device operation. Two Gigabit Ethernet MACs (10/100/1000 Mbps) are on-chip; the PHY interface is RGMII/RMII, so an external PHY chip is still required for the magnetics.
Package, footprint, and temperature grade
The operating junction temperature range is 0°C to 90°C, which covers indoor and most industrial enclosures but not extended outdoor or automotive under-hood environments. Surface-mount only; the package is supplied in tray format. The MSL level is not listed in this record, but the 324-NFBGA typically requires MSL 3 handling — bake before reflow if the moisture barrier bag has been open longer than the floor life.
Peripheral set and security features
Additional interfaces include CAN, I2C, McASP (audio serial port), McSPI, MMC/SD/SDIO, and UART. The McASP supports up to four serial data pins, which is enough for I2S or TDM audio streams. The MMC/SD/SDIO controller handles eMMC and SD cards up to the high-speed SDR mode. On-chip security features include a cryptographic accelerator and a random number generator. These are accessible through the device's secure boot chain — the ROM loader checks the signed image before releasing the core.
Production status and compliance
The part is ROHS3 compliant.