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Texas Instruments AM3351BZCE30 — Interface & Transceivers

AM3351BZCE30 Texas Instruments Sitara ARM Cortex-A8, 300MHz

MPNAM3351BZCE30
End of Life

Texas Instruments Sitara™ AM3351BZCE30 ARM Cortex-A8 microprocessor, 300MHz, USB 2.0 + PHY, Gigabit Ethernet, 298-NFBGA tray.

$12.39Ref. price · indicative, final on quote
Packaging298-LFBGA
RoHSROHS3 Compliant
SeriesSitara™
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

AM3351BZCE30 specifications
ParameterValue
SeriesSitara™
MountingSurface Mount
Voltage - i (O)1.8V, 3.3V
Additional interfacesI2C, McASP, McSPI, MMC/SD/SDIO, UART
Display & interface controllersLCD, Touchscreen
Operating temperature0°C ~ 90°C (TJ)
Number of cores (Bus width)1 Core, 32-Bit
USBUSB 2.0 + PHY (1)
Speed300MHz
PackageTray
Ethernet10/100/1000Mbps (1)
Core processorARM® Cortex®-A8
Case298-LFBGA
RAM controllersLPDDR, DDR2, DDR3, DDR3L
Co-Processors (DSP)Multimedia; NEON™ SIMD
Security featuresCryptography, Random Number Generator
Graphics accelerationYes

Product details

Core compute and integration for connected control

The AM3351BZCE30 is a single-core ARM Cortex-A8 microprocessor from the Sitara family, clocked at 300 MHz with a 32-bit bus width and a NEON SIMD coprocessor for multimedia acceleration. It integrates a USB 2.0 port with on-chip PHY and a 10/100/1000 Mbps Ethernet MAC with its own PHY, so a two-interface board (USB device + Gigabit Ethernet) needs no external transceiver for the MAC side. Memory controller supports LPDDR, DDR2, DDR3, and DDR3L — the same PCB layout can serve a cost-optimised DDR2 build or a higher-bandwidth DDR3 design by swapping the memory devices and adjusting the termination.

Peripheral set and security for industrial HMI

Additional interfaces include I2C, McASP, McSPI, MMC/SD/SDIO, and UART, covering the typical sensor bus, audio codec, and SD-card storage needs of a panel-mounted HMI or gateway. On-chip display and touchscreen controllers drive an LCD panel directly, and the graphics acceleration block offloads 2D compositing from the Cortex-A8 core. A hardware security block with cryptography and a random number generator supports secure boot and encrypted communication without loading the main CPU.

Package, temperature, and compliance

I/O voltage rails are 1.8 V and 3.3 V, matching common DDR and peripheral supplies without external level shifters on most interfaces.