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Texas Instruments AM2634CODFHAZCZR — Microcontrollers & Processors (MCU / MPU / DSP)

TI AM2634CODFHAZCZR Sitara MCU, Quad Cortex-R5F, 400 MHz

MPNAM2634CODFHAZCZR
End of Life

Texas Instruments Sitara™ AM2634CODFHAZCZR, quad-core 32-bit ARM Cortex-R5F MCU, 400 MHz, 2M x 8 SRAM, 256 KB TCM, 140 I/O, 324-NFBGA, -40 to 105°C.

$20.06Ref. price · indicative, final on quote
Packaging324-LFBGA
RoHSROHS3 Compliant
SeriesSitara™
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

AM2634CODFHAZCZR specifications
ParameterValue
SeriesSitara™
MountingSurface Mount
Oscillator typeInternal
Program memory typeTightly Coupled Memory (TCM)
Voltage - supply (Vcc (Vdd))1.14V ~ 1.26V
Operating temperature-40°C ~ 105°C (TJ)
Speed400MHz
PackageTape & Reel (TR); Cut Tape (CT)
RAM size2M x 8
Core size32-Bit Quad-Core
PeripheralsAES, DMA, POR, PWM, SHA, TRNG, WDT
ConnectivityCANbus, Ethernet, I²C, MMC/SDIO, QSPI, SPI, UART/USART
Number of i (O)140
Core processorARM® Cortex®-R5F
Case324-LFBGA
Data convertersA/D 6x12b SAR; D/A 1x12b
Program memory size256KB (256K x 8)

Product details

Quad-core real-time control at 400 MHz

The AM2634CODFHAZCZR packs four ARM Cortex-R5F cores running at 400 MHz — this is a deterministic real-time processor, not a general-purpose application MPU. The Cortex-R5F supports split/lock mode, meaning two cores can run independently or lockstep for safety-critical redundancy without an external supervisor.

On-chip memory architecture for time-critical loops

2 MB of SRAM (2M x 8) and 256 KB of Tightly Coupled Memory (TCM) give the firmware engineer deterministic access to code and data — TCM runs at core speed with single-cycle latency, which is the difference between meeting a 1 µs PWM update window and missing it. The 256 KB TCM can hold the entire interrupt service routine stack for a multi-axis servo drive without cache thrash.

Industrial connectivity and analog integration

CAN-FD, Ethernet, and QSPI on the peripheral list — the CAN-FD ports handle real-time fieldbus traffic (EtherCAT or PROFINET gateways typically sit on the Ethernet MAC), while the QSPI interface connects to external NOR flash for boot or firmware-over-the-air staging. Six 12-bit SAR ADC channels and one 12-bit DAC let the MCU sample motor phase currents and output an analog setpoint without an external converter. 140 GPIOs in the 324-ball BGA — enough to drive a parallel address bus to an FPGA or sample 40 encoder channels with index capture.

Temperature grade and package reality

The 324-NFBGA (15x15 mm) package has a 0.80 mm ball pitch, which is routable on a 4-layer board with blind vias; a 6-layer stack-up gives cleaner signal integrity for the Ethernet differential pairs and the high-speed QSPI clock. The supplier device package is 324-NFBGA, which means the balls are on a 0.80 mm grid and the die is exposed through the backside for thermal dissipation. A thermal pad under the BGA with at least 9 thermal vias to the ground plane keeps the junction below 105°C at full 400 MHz load.

Sourced through authorized and independent distribution channels. The tape-and-reel packaging means it ships on 13-inch reels; cut tape is available for prototyping quantities.

Frequently asked questions

What is the closest pin-compatible alternative to AM2634CODFHAZCZR?

The AM2634 is a specific quad-core Cortex-R5F variant in the Sitara family; a different package or core count would require a board layout change. Contact your TI field applications engineer for a parametric cross if you need a second source.

What compliance documentation does Texas Instruments provide for AM2634CODFHAZCZR?

The part is ROHS3 compliant per TI's lifecycle record. TI typically provides a Declaration of Conformity and material declaration upon request through their compliance portal.