Active-production 14-bit SAR ADC at 65 MSPS — fit and interface
The ADC3543IRSBT is a single-channel 14-bit successive-approximation-register (SAR) analog-to-digital converter sampling at 65 MSPS, built for applications that need a high-speed, low-latency conversion path without the pipeline delay of a sigma-delta architecture. Accepts both differential and single-ended inputs, with the choice of an external or internal voltage reference — the internal reference simplifies the BOM for a single-channel design, while an external reference lets you match the full-scale range to the sensor's output swing. Serial SPI interface keeps the digital pin count to four lines (SCLK, SDI, SDO, CS) — a natural fit for FPGAs and MCUs with limited GPIO. The 65 MSPS throughput is the per-sample conversion rate; the SPI clock must sustain at least 14 bits per sample plus overhead, which at 65 MSPS demands an SCLK above 1 GHz — so a parallel interface would be faster, but the serial interface saves board space and routing layers on the digital side.
Supply rails and temperature — single-voltage convenience with industrial range
Both analog and digital supply rails run from a single 1.75 V to 1.85 V supply — no separate AVDD and DVDD rails to sequence. This simplifies the power tree: a single 1.8 V rail (common in FPGA and ASIC systems) powers the ADC, and the digital I/O is also at 1.8 V, so it interfaces directly with 1.8 V logic without a level translator.
Sourcing posture — active part, no obsolescence risk
The part is ROHS3 compliant and free of the six restricted substances under the current EU RoHS directive.