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Texas Instruments 74ACT11373DWR — Logic ICs

74ACT11373DWR TI 8-bit D Latch, 8.5ns, 24-SOIC

MPN74ACT11373DWR
End of Life

Texas Instruments 74ACT series D-Type Transparent Latch, 8:8 circuit, Tri-State outputs, 8.5ns propagation delay, 24-SOIC (0.295", 7.50mm Width), Surface Mount, Tape & Reel.

$3.36Ref. price · indicative, final on quote
Packaging24-SOIC (0.295", 7.50mm Width)
RoHSROHS3 Compliant
Series74ACT
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

74ACT11373DWR specifications
ParameterValue
Series74ACT
Logic typeD-Type Transparent Latch
Output typeTri-State
MountingSurface Mount
Voltage4.5V ~ 5.5V
Current - output high, low24mA, 24mA
Operating temperature-40°C ~ 85°C
Circuit8:8
PackageTape & Reel (TR); Cut Tape (CT)
Case24-SOIC (0.295\", 7.50mm Width)
Independent circuits1
Delay time - propagation8.5ns

Product details

8-bit transparent latch with tri-state bus hold

The Texas Instruments 74ACT11373DWR is an 8-bit D-type transparent latch with tri-state outputs, packaged in a 24-SOIC (300-mil wide body) for surface-mount assembly. It belongs to the 74ACT logic family, offering a balance of speed and drive for bus-oriented designs. Propagation delay is 8.5 ns typical, and the device can source or sink 24 mA per output — enough to drive a lightly loaded address or data bus without external buffers.

A single independent latch circuit handles the full 8-bit word — the latch-enable (LE) pin gates the data flow, and the output-enable (OE) pin puts the bus into high-impedance state when deasserted.

Package and board-fit note

The 1.27 mm pitch is layout-friendly on two-layer boards — no micro-via or buried via needed for fan-out.

Lifecycle and compliance

Sourced to order against BOM quantities; availability and current pricing confirmed at RFQ through independent distribution channels.

Frequently asked questions

What is the propagation delay of the 74ACT11373DWR?

The typical propagation delay is 8.5 ns. This figure is the time from the latch-enable (LE) or data (D) input transition to the output (Q) change, measured under standard test conditions.