120 MHz RXv2 core with 1 MB flash — memory headroom for dual-image OTA
The R5F565N9BGFB#30 is a 32-bit RX65N microcontroller built around the RXv2 core running at 120 MHz. The 1 MB on-chip flash (1M x 8) paired with 256K x 8 SRAM leaves room for a dual-bank firmware update strategy — one image active, one staged — without external memory for most industrial protocol stacks.
Peripheral set for networked control — CAN, Ethernet, USB, QSPI
Connectivity includes CANbus, Ethernet, USB, I²C, SPI, SCI, UART/USART, and QSPI — enough to serve as the main controller in a motor drive with EtherCAT slave or a remote I/O node with CANopen. The 111 GPIOs in the 144-LQFP package give headroom for parallel LCD or external memory bus (EBI/EMI) without sacrificing serial interfaces. On-chip data converters: 29-channel 12-bit ADC and 2-channel 12-bit DAC. The ADC count covers three-phase current sensing plus auxiliary inputs (temperature, DC bus voltage) in a single chip. Peripherals include DMA, LVD (low-voltage detect), POR, PWM, and WDT — the LVD and POR eliminate external supervisor ICs in cost-sensitive designs.
Industrial temperature grade and package — board-fit constraints
The 144-LQFP (20x20 mm body) with 0.5 mm pitch demands a 4-layer PCB for fan-out of the inner rows — a 2-layer board will not route all 111 I/O cleanly. No separate I/O or analog supply required, though the ADC accuracy benefits from a clean analog rail via the AVCC pin.
ROHS3 compliant, no substance restrictions for EU or global markets.