RXv2 core at 48 MHz — what the clock buys you
The RXv2 core in the R5F51405AGFL#30 runs at 48 MHz with a single-cycle multiply-accumulate path — that is the throughput ceiling for a FIR filter loop or a sensor-compensation polynomial. The internal oscillator means you skip the external crystal for the boot clock; step through the boot ROM to confirm the main clock source before the PLL locks.
128 KB flash / 32 KB RAM / 8 KB EEPROM — firmware budget split
The 8 KB of dedicated EEPROM (8K x 8) stores calibration parameters and fault logs without wearing the main flash sectors.
Peripheral set for HMI and motor-control nodes
On-chip capacitive touch sensing, a 12-bit ADC with 11 channels, PWM timers, CAN, I²C, SCI, and SPI — this covers a control panel with a touch interface, a CANopen fieldbus link, and a sensor array. The 48-LQFP package (7x7 mm, 0.5 mm pitch) routes comfortably on a 4-layer board; the ADC channels need clean analog ground under the LFQFP paddle.