NXP Semiconductors PBSS4230PANP,115 — Memory (DRAM / SRAM / Flash / EEPROM)
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NXP Semiconductors / Memory (DRAM / SRAM / Flash / EEPROM)

PBSS4230PANP,115 NPN/PNP transistor, 2A, 30V, 6-HUSON

MPN PBSS4230PANP,115
End of Life Spot Stock · 24-48h Dispatch 100% Original Sealed

NXP Semiconductors PBSS4230PANP,115 dual NPN/PNP transistor, 2A collector current, 30V Vce breakdown, 120MHz transition frequency, 6-HUSON (2x2) surface mount package, Bulk.

In Stock: 21,000 pcs
MOQ: 1 pcs
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[SPEC] Essential Parameters Snapshot Full Specifications (12)
Package / Case 6-UFDFN Exposed Pad

Full Technical Specifications

12 Parameters
PBSS4230PANP,115 specifications
Parameter / AttributeSpecification / Value
MountingSurface Mount
FET typeNPN, PNP
Voltage - collector emitter breakdown30V
Current - collector (Ic)2A
Current - collector cutoff100nA (ICBO)
DC current gain (hFE) (Min) @ ic, vce200 @ 1A, 2V
Power - max510mW
Frequency - transition120MHz
Operating temperature150°C (TJ)
PackageBulk
Case6-UFDFN Exposed Pad
Vce saturation (Max) @ ib, ic290mV @ 200mA, 2A
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Technical Details & Description

Dual-transistor BOM consolidation in a single 2x2 mm package

The PBSS4230PANP,115 packs both an NPN and a PNP transistor into one 6-HUSON (2x2) package, cutting the component count for push-pull drivers, H-bridge pre-drivers, and level translators. Each side handles 2 A continuous collector current with a 30 V Vce breakdown, so it drives small relays, solenoids, and logic-level loads directly from a 24 V supply rail. The 120 MHz transition frequency means it switches comfortably in the 100 kHz to 1 MHz range for DC-DC converter gate drive or Class-D audio pre-drive — the speed limit is set by the load capacitance and base drive, not the die itself.

Low saturation voltage and high gain reduce thermal stress

Vce(sat) is just 290 mV at 200 mA base current and 2 A collector current — conduction loss at 2 A is under 0.6 W, which the 510 mW package rating can handle only with the exposed pad soldered to a copper plane. Without the pad thermal path, the junction temperature climbs above the 150°C (TJ) limit at full load. DC current gain (hFE) is a minimum of 200 at 1 A collector current and 2 V Vce — this means a microcontroller GPIO sourcing just 5 mA can saturate the transistor at 1 A load, eliminating the need for a separate driver stage in low-side switching applications. Collector cutoff current is max 100 nA (ICBO) — negligible leakage in battery-powered circuits where the load is switched off for long periods.

Package footprint and reflow considerations

The 6-UFDFN Exposed Pad package (6-HUSON, 2x2 mm) has a 0.5 mm pitch — the centre pad must be soldered to a thermal via array under the part to pull heat into the inner copper layers. Without the via pattern, the 510 mW dissipation limit derates sharply above 25°C ambient. The Bulk packaging means parts arrive in tubes or trays, not tape-and-reel — plan for manual or tube-fed placement; no reel changeover on the pick-and-place line.

Active production — no end-of-life concerns for new designs

The 150°C (TJ) junction temperature rating aligns with industrial temperature environments — motor-drive enclosures, power-supply hot spots, and automotive under-hood zones where ambient hits 105°C still leave 45°C margin before the die limit.

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