Kinetis K10 MK11DX256AVMC5 — ARM Cortex-M4 at 50 MHz with integrated EEPROM
Connectivity includes I²C, IrDA, SPI, and UART/USART interfaces. It is supplied in a 121-ball MAPBGA (8x8 mm) package with 64 general-purpose I/O lines.
The 32 KB RAM is enough for moderate data buffers; if your application needs larger frame buffers or double-buffered graphics, budget for external SRAM or a part from the Kinetis K6x family with more on-chip RAM.
Integrated EEPROM — one less external part
The 4 KB EEPROM block (4K x 8) is a genuine EEPROM array, not Flash emulated, so it supports byte-wise writes and the full rated endurance without wear-leveling overhead. This saves a separate serial EEPROM on the BOM and frees two I²C or SPI pins. Calibration constants, node IDs, and fault logs live here without consuming Flash program space.
121-MAPBGA footprint — layout notes
The 121-ball MAPBGA (8x8 mm) package is supplied.
It is ROHS3 compliant.