16-bit buffer for mixed-voltage bus interfaces
The Nexperia 74LVC16244ADGG,112 is a 16-bit non-inverting buffer with 3-state outputs, organized as four independent 4-bit sections. The 48-TSSOP package (0.240" body width) keeps the board footprint compact for dense layouts.
Supply voltage range and logic compatibility
Rated for 1.2V to 3.6V, this buffer accepts standard 3.3V and 1.8V logic levels without external level shifters. The 3.6V upper limit also covers 2.5V and 3.0V rails common in FPGA and SoC I/O banks. At 3.3V the 24mA drive holds its output voltage within a few hundred millivolts of the rail under full load, preserving noise margin on a backplane or ribbon cable.
The wide range also covers cold-start conditions in unheated enclosures.