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NXP Semiconductors 74AHCT2G241DP125 — Logic ICs

74AHCT2G241DP125 Nexperia 74AHCT Dual Buffer, 4.5-5.5V

MPN74AHCT2G241DP125
End of Life

Nexperia 74AHCT series, Buffer, Non-Inverting, 2-Element, 1-Bit per element, 3-State output, 8-TSSOP/8-MSOP, 4.5V-5.5V supply, -40°C to 125°C.

$0.18Ref. price · indicative, final on quote
Packaging8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
StockContact for availability
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
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Specifications

74AHCT2G241DP125 Technical Specifications
ParameterValue
Series74AHCT
Logic typeBuffer, Non-Inverting
Output type3-State
Mounting typeSurface Mount
Voltage4.5V ~ 5.5V
Current - output high, low8mA, 8mA
Operating temperature-40°C ~ 125°C (TA)
PackageBulk
Case8-TSSOP, 8-MSOP (0.118\", 3.00mm Width)
Number of elements2
Number of bits per element1

Product details

Dual buffer for 5 V bus interface

The Nexperia 74AHCT2G241DP125 is a dual non-inverting buffer with 3-state outputs, designed for 5 V logic systems.

Supply and temperature — what matters for the BOM

The 4.5 V minimum supply ensures compatibility with 5 V TTL levels; the part will not run at 3.3 V. If the board has a mixed-voltage backplane, this buffer stays on the 5 V rail only. The 125 °C maximum junction temperature matches the AEC-Q100 Grade 1 requirement for under-hood automotive modules. No separate AEC qualification is listed on this variant, but the temperature grade is the same.

Package and footprint

The part is offered in an 8-TSSOP or 8-MSOP package (3.00 mm width), both surface-mount. The supplier device package listed is 8-TSSOP. The dual-element, 1-bit-per-element layout means only two data lines per package — a clean fit for point-to-point buffering on a small board.

Frequently asked questions

Is 74AHCT2G241DP125 a dual buffer?

Yes, it contains two independent non-inverting buffer elements, each with a single-bit input and 3-state output.