The Micron MT55L256L18P1F-10 is a 4 Mbit ZBT (Zero Bus Turnaround) synchronous SRAM organized as 256K x 18 bits. It is designed for high-throughput applications where back-to-back read and write cycles must occur without dead cycles — think packet buffers in network switches, cache in telecom line cards, or look-up tables in FPGA-based accelerators. The 5 ns access time and 100 MHz clock rate let it keep pace with a 100 MHz bus without wait states, so timing closure on a high-speed memory interface is straightforward.
Package and mounting — 165-ball FBGA
It is surface-mount only — no socket option.
For volume BOM commitments, an RFQ is the right next step.