133 MHz SPI — what it buys the bus
At 133 MHz, the SPI interface delivers a sustained read throughput that keeps a modern Cortex-R or Cortex-M core fed during XIP (eXecute-In-Place) boot sequences. The page program time of 2.8 ms and block erase time of 8 ms per 64 KB sector mean the write-side is adequate for OTA update staging but not for high-frequency data logging — plan a small RAM buffer if the application writes more than a few sectors per second.
Lifecycle and supply position
Listed as Active in production. ROHS3 compliant. There is no announced EOL or LTB notice on this line. For BOM freeze and PCN watch, the Automotive series typically sees longer product life than commercial equivalents — Micron maintains NOR Flash production for automotive customers on multi-year supply commitments. Sourced and quoted to order against an RFQ through independent distribution; availability and current pricing confirmed at quote time.