PCI bus controller in a PBGA-352 footprint
The OR3TP127BA352-DB is a Lattice ORCA™ OR3TP12 FPGA hard-wired as a PCI bus controller — 60,000 gates and 187 I/O in a 352-ball PBGA. The 3 V supply rail is the core voltage; the PCI bus interface on the I/O banks handles 3.3 V signalling per the PCI Local Bus spec, so the board needs a separate 3.3 V rail for the I/O buffers if the core runs at 3.0 V. The 32 Kbit on-chip block RAM is sized for PCI target FIFOs or a small configuration scratchpad — not for large frame buffers. The 2016 logic cells implement the PCI target or master state machine plus local address decode without external CPLD glue.
Active lifecycle — no EOL pressure
The commercial temperature grade (0°C to 70°C) limits deployment to indoor, climate-controlled environments — no extended temp or automotive qualification on this variant.
Package — PBGA-352 board integration
The 352-ball PBGA (27 mm × 27 mm typical for this ball count) demands a multi-layer PCB for fan-out — the 187 I/O plus power and ground balls require at least four signal layers to route without via congestion under the package. Package type is Bulk — loose trays or tubes, not tape-and-reel. For reflow, the PBGA's moisture sensitivity level should be verified from the latest Lattice PBGA handling note before opening the dry-pack.
Sourcing — quoted to order
For a single-source FPGA like this, a bridge-buy or last-time-buy hedge is worth discussing at RFQ if the production run extends beyond 12 months.