Logic fabric and I/O budget for the BOM line
The OR2T26A6BA352-DB belongs to the ORCA™2 family, delivering 63,600 gates and 2,304 logic elements/cells — enough for medium-density glue logic, bus bridging, or control-path sequencing in an FPGA-based design. 384 user I/O on this package gives substantial headroom for wide data buses, parallel memory interfaces, or multi-channel sensor arrays. The I/O count is the first fit check against the board's netlist — if the design needs more than 384 signal pins, a larger FPGA is required. On-chip block RAM totals 36,864 bits — sized for small FIFOs, look-up tables, or coefficient storage. Designs that exceed this budget must use external SRAM or SDRAM off-chip, adding BOM cost and PCB routing complexity.
Supply rail and temperature envelope
Core and I/O run from a single 3 V supply rail — no separate VCCIO or VCCAUX needed. This simplifies the power tree to one regulated 3.0 V rail, but the designer must confirm the 3 V logic levels are compatible with the rest of the system (3.3 V devices may need a level translator on output pins). Not qualified for industrial or automotive ambient ranges.
Package and procurement note
Supplied in Bulk format — loose units, not tape-and-reel. For automated pick-and-place, the buyer should confirm the feeder compatibility or arrange tray/tube repackaging at the distributor level. Surface Mount package — the exact footprint dimensions and ball/pad layout are in the Lattice datasheet. No pin-compatible replacement exists across the ORCA2 family; a board spin is required to migrate to a different I/O count or package.