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Lattice Semiconductor LFCPNX-100-7CBG256C — FPGA / CPLD & Programmable Logic

LFCPNX-100-7CBG256C Lattice CertusPro-NX FPGA 96K LE 169 I/O

MPNLFCPNX-100-7CBG256C
Active

Lattice Semiconductor CertusPro-NX series FPGA, order code LFCPNX-100-7CBG256C, 96,000 logic elements, 3,833,856 total RAM bits, 169 user I/O, 0.95 V core, 0°C to 85°C TJ, 256-ball WLP, tray.

$81.19Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

LFCPNX-100-7CBG256C specifications
ParameterValue
SeriesCertusPro™-NX
MountingSurface Mount
Operating temperature high0°C to 85°C (TJ)
Package_typeTray
Number of i (O)169
Total ram bits3833856
StatusActive
Supply voltage0.95
Number of labs (Clbs)24000
Number of logic elements (Cells)96000

Product details

96,000 logic elements in a 256-ball WLP

The LFCPNX-100-7CBG256C is a CertusPro-NX FPGA from Lattice Semiconductor packing 96,000 logic elements and 3,833,856 total RAM bits in a 256-ball wafer-level package. The 0.95 V core supply keeps dynamic power in check for mid-density edge compute, sensor fusion, and bridge functions. With 169 user I/O the package delivers a high I/O-to-ball ratio — useful when the design needs many parallel lanes without jumping to a larger BGA.

Lifecycle status is Active, meaning Lattice continues to manufacture and support the part through standard distribution.

Logic capacity vs. sibling FPGAs

Compared to the ECP3-series LFE3-70EA-7FN484C (67,000 logic elements, 4.5 Mbit RAM), the CertusPro-NX offers 43% more logic fabric and a smaller 256-ball package. The ECP5-series LFE5UM-45F-8BG381C (44,000 logic elements, 1.99 Mbit RAM) sits a full density tier below. The 0.95 V core of the CertusPro-NX is lower than the 1.14 V and 1.045 V rails of the ECP3 and ECP5 siblings, which shifts the power budget downward for the same gate count.

Sourcing and package details

Supplied in tray, surface-mount. The 256-ball WLP footprint requires a controlled solder-paste stencil and a reflow profile matched to the wafer-level package — no separate substrate, so the ball coplanarity is set at the wafer fab. The 0.95 V core rail must be clean; Lattice recommends a dedicated regulator with <30 mV ripple at the FPGA supply pins.