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Lattice Semiconductor Corporation ICE40UP5K-SG48I — FPGA / CPLD & Programmable Logic
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RoHS Compliant · Lead-Free EIA-481 Standard
Lattice Semiconductor Corporation / FPGA / CPLD & Programmable Logic

Lattice ICE40UP5K-SG48I FPGA, 5280 LEs, 39 I/O, 48-QFN

MPN ICE40UP5K-SG48I
Active Spot Stock · 24-48h Dispatch 100% Original Sealed

Lattice Semiconductor Corporation iCE40 UltraPlus™ FPGA, ICE40UP5K-SG48I, 5280 logic cells, 39 I/O, 1.17 Mbit block RAM, 48-VFQFN exposed pad, 1.14-1.26 V supply, -40 to 100°C.

In Stock: 153 pcs
MOQ: 1 pcs
Logistics: DHL / FedEx DAP (Global Express · 3-7d) Russia & CIS DDP (Door-to-Door Cleared)
Dispatch: Shenzhen / HK
Unit Price (USD)
$12.61 / pc
Direct Purchase Ready
Volume Pricing Breaks Confirmed upon quotation
1+ pcs
$12.61
10+ pcs
$10.89
30+ pcs
$9.96
100+ pcs
$9.18
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$12.61 / ea

153 in stock — maximum per order · 3–4 days lead time

$10.89 / ea from 10 pcs
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100% Original Sealed 45x Microscope QC 30-Day Warranty · COC USD T/T & PI · DAP/DDP
[SPEC] Essential Parameters Snapshot Full Specifications (10)
Package / Case 48-VFQFN Exposed Pad
Supply Voltage 1.14V ~ 1.26V
ALT
Facing long factory lead times or allocation on ICE40UP5K-SG48I? Verified pin-compatible alternatives available with active Shenzhen stock and 100% solder-ready footprint match.
View Pin Alternates (3)

Full Technical Specifications

10 Parameters
ICE40UP5K-SG48I specifications
Parameter / AttributeSpecification / Value
SeriesiCE40 UltraPlus™
MountingSurface Mount
Supply voltage1.14V ~ 1.26V
Operating temperature-40°C ~ 100°C (TJ)
PackageTape & Reel (TR) Cut Tape (CT)
Number of i (O)39
Case48-VFQFN Exposed Pad
Total RAM bits1171456
Number of LABs (CLBs)660
Number of logic elements (Cells)5280
100% Footprint Match · Solder-Ready (No PCB Redesign Needed)

Need Stock or a Drop-in Second-Source for ICE40UP5K-SG48I?

Package: QFN / ucBGA / WLCSP / TQFP · Pin-compatible replacements with immediate Shenzhen spot stock

Footprint Match 97%
Supply Chain & Allocation Reality:

The iCE40 line is the FPGA family that the hobby and small-batch world actually uses - and the data says the same thing about buyers: searches concentrate on Lattice CPLD and iCE40 class parts while Xilinx orderables sit at the noise floor. The family is five sub-splits with wildly different capabilities (UltraLite to UltraPlus) sharing a naming theme and a common trait: an SRAM fabric that must be loaded at every power-up - from an external SPI flash, a host CPU, or the family-internal NVCM. The sourcing consequence is structural: an iCE40 socket is never just an FPGA line on the BOM; it is a two-part relationship with a configuration memory.

Verified Pin-Compatible Replacements (3 verified alternatives)

iCE40UP5K Lattice Semiconductor QFN-48 / SG48 / WLCSP
Functional Equivalent
Availability & Target Pricing:

The UltraPlus Flagship

Shenzhen Spot Stock (24-48h Dispatch)

Electrical & Core Specs:

The richest sub-split: 5,280 LUTs with 1Mb of SPRAM (four 256kb blocks), DSP blocks, two hardened SPI and two I2C blocks, and on-chip oscillators - built for always-on sensor buffering and audio pre-processing.

Low-power single-rail design point; the UltraPlus is the part behind most current iCE40 designs.

Compatibility & Drop-In Notes: Sub-splits are not interchangeable: LP/HX/Ultra/UltraLite/UltraPlus differ in logic, memory and hardened IP. Replacing one with another is a re-synthesis and placement project, and the pin maps differ even in the same package size.
Package & Solder Footprint: Common QFN-48-class outlines are shared - verify pin map against the exact device, not the package.
Shenzhen Warehouse Stock & MOQ: Stocked with config flash paired on request (W25Q-class SPI flash sourced on the same order).
Request Volume Quote for iCE40UP5K Compare ICE40UP5K-SG48I vs iCE40UP5K Spec Matrix
iCE40HX1K Lattice Semiconductor TQFP-144 / VQFP-100 / QFN
Functional Equivalent
Availability & Target Pricing:

The Performance Sub-Split

Shenzhen Spot Stock (24-48h Dispatch)

Electrical & Core Specs:

The HX line trades standby current for more logic per die (HX1K/4K/8K against LP1K/4K/8K); the classic hobby board part of the iCE40 generation.

Low-power but not the micropower LP class; check the static current against the design budget.

Compatibility & Drop-In Notes: LP and HX are the two faces of the same generation: the pin maps match within a device size, but the power and clocking characteristics differ. In repair of hobby-era boards, match the exact device.
Package & Solder Footprint: Larger through-hole-friendly VQFP/TQFP outlines exist in this line.
Shenzhen Warehouse Stock & MOQ: Stocked for repair of the hobby and education ecosystem boards.
Request Volume Quote for iCE40HX1K Compare ICE40UP5K-SG48I vs iCE40HX1K Spec Matrix
ECP5 Lattice Semiconductor caBGA / csBGA families
Functional Equivalent
Availability & Target Pricing:

The Step-Up Platform

Shenzhen Spot Stock (24-48h Dispatch)

Electrical & Core Specs:

The next class above iCE40 in the Lattice stack: higher logic density and hardened high-speed interfaces for video, networking and instrumentation designs.

Multi-rail FPGA supply design - not a drop-in to any iCE40 socket.

Compatibility & Drop-In Notes: Listed to complete the Lattice map - the two families share tooling (Lattice Radiant) but nothing electrical. The honest cross-family statement: re-design, not replacement.
Package & Solder Footprint: BGA-only packaging; assembly and inspection requirements differ from iCE40 QFN work.
Shenzhen Warehouse Stock & MOQ: Stocked per part number with photographed markings - BGA FPGAs are a favored relabeling target.
Request Volume Quote for ECP5 Compare ICE40UP5K-SG48I vs ECP5 Spec Matrix
Buyer & Quality Checklist for Sourcing Alternatives
  • Every iCE40 is SRAM-based: the design lives in configuration memory loaded at power-up (external SPI flash, host controller, or NVCM where present). A board without its config flash is a board with a blank FPGA - when sourcing iCE40, source the paired W25Q-class flash on the same order.
  • The five sub-splits (UltraLite / LP / HX / Ultra / UltraPlus) are different devices, not grades of one device: logic, memory, DSP and hardened IP differ, and the same-size package does not imply the same pin map.
  • Small packages drop features: several mini outlines have no PLL, and the constant-current LED sink exists on selected packages only. The package letter in the orderable number is a spec, not a shipping choice.
  • NVCM configurations are instant-on and secure but one-shot - production planning for NVCM-programmed devices needs lead time and programming decisions upstream, not at the bench.
  • The market leans Lattice for this class (buyer searches concentrate here, not on Xilinx orderables): keep depth in iCE40 and the config flash, with ECP5 quoted case-by-case.
  • iCE40 boards in the repair channel are numerous (hobby, education, instrumentation): the two failure parts are the FPGA and its config flash - check the flash first, it is cheaper and it holds the bitstream.
Frequently Asked Technical Questions

Q: Which iCE40 sub-family do I need?

A: Choose by need: UltraPlus (UP5K) when on-chip SPRAM or DSP is required; HX/LP for general low-power logic with more density; Ultra for mobile glue logic with hardened SPI/I2C; UltraLite for the absolute smallest always-on designs. Sub-splits are not interchangeable.

Q: Does iCE40 need an external flash chip?

A: It configures at every power-up: from an external SPI flash in self-boot mode, from a host CPU in slave mode, or from the internal NVCM where the design was programmed there. Most boards carry a small W25Q-class SPI flash for the bitstream - source it with the FPGA.

Q: Can I replace a dead iCE40 with an ECP5?

A: No - different family, different packaging and supply design. ECP5 is the step-up platform for higher density and interfaces; migrating is a re-layout and re-synthesis project.

Technical Details & Description

Logic density and on-chip memory for sensor fusion and display bridging

The ICE40UP5K-SG48I: The 39 user I/O, brought out to a 48-QFN with a 7x7 mm body and exposed thermal pad, suit this part for sensor aggregation or display-bridge roles where board area is tight and the thermal path to the ground plane matters.

Supply rails and temperature grade for industrial edge duty

Core supply is 1.14 V to 1.26 V — a 1.2 V rail with ±5 % regulation keeps the FPGA within spec. The 48-VFQFN exposed pad (7x7 mm) requires a thermal via array under the paddle to pull heat into the inner-layer copper pour; the datasheet's recommended footprint keeps the junction below 100 °C at full toggle rate.

Frequently asked questions

Will ICE40UP5K-SG48I drop into a board designed for ICE40UP3K-UWG30ITR1K without rewiring?

No — the UP5K comes in a 48-QFN (7x7 mm) with 39 I/O, while the UP3K uses a 30-ball WLCSP (2.6x2.9 mm) with 21 I/O. The package footprint and ball-out are completely different; a board spin is required.

What compliance documentation does Lattice provide for ICE40UP5K-SG48I?

Lattice certifies ROHS3 compliance per the product status. Full material declaration, REACH SVHC disclosure, and conflict-minerals reporting are available through the Lattice compliance portal.

ICE40UP5K-SG48I
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