Lattice Semiconductor has marked the GAL22V10D-25LJNI as Obsolete. This means the manufacturer no longer produces the device, and no official last-time-buy window remains open.
Parametric profile — 10 macrocells, 25 ns propagation delay
The GAL22V10D-25LJNI is an EE PLD from the GAL®22V10 family, offering 10 macrocells with a maximum propagation delay (tpd) of 25 ns. This delay sets the ceiling for combinatorial logic paths — a 25 ns tpd means the output settles within 25 ns of the input transition, which limits the system clock to roughly 40 MHz in a single-level logic path. The EE PLD programmable type means the configuration is stored in EEPROM cells and retains the logic pattern through power cycles. Housed in a 28-PLCC (J-Lead) package with a body size of 11.51 x 11.51 mm, the device is surface-mount and suits board-level assembly where the J-bend lead provides a compliant solder joint under thermal cycling.
Board-fit and temperature grade
The 28-PLCC footprint is a common legacy package; the J-lead profile allows socketed or soldered mounting, though the part is surface-mount only. The EE PLD technology draws static power proportional to the macrocell count — 10 macrocells keep the quiescent current low enough for most 5 V backplanes.