Logic capacity and timing — 10 macrocells at 20 ns tpd
The GAL22V10D-20LPNI: This 20 ns pin-to-pin delay sets the ceiling for registered operation — a 50 MHz clock is the practical limit before setup violations appear, assuming balanced routing and a single register per macrocell. The 10 macrocells each contain a programmable flip-flop (D/T/JK/SR) and configurable output polarity, giving 10 registered or combinatorial outputs in a 24-pin DIP. For a glue-logic replacement or a state machine with fewer than 10 states, this part fits without wasting fabric — every macrocell counts when you are retrofitting a legacy board.
Industrial temperature grade and 5 V supply rail
The 24-PDIP (0.300-inch body) through-hole package is the original DIP footprint — no adapter board needed when replacing a 24-pin PAL or GAL on an existing PCB. The tube packaging means the parts arrive in anti-static tubes, not tape-and-reel; expect 15 to 20 devices per tube depending on the supplier's pack quantity.
Lattice Semiconductor has marked the GAL22V10D-20LPNI as Obsolete. Each lot is sourced and verified against the BOM quantity at RFQ time — no standing inventory is held.