10 macrocells, 20 ns — the speed-grade fit for legacy glue logic
The Lattice GAL22V10D-20LPI is a GAL®22V10-series EE PLD with 10 macrocells and a maximum propagation delay (tpd) of 20 ns. The 20 ns tpd rating means combinatorial inputs settle within 20 ns of the clock edge — fast enough for 50 MHz address decoding or state-machine sequencing in legacy 5 V bus architectures.
Obsolete — sourcing through independent surplus channels
Lattice Semiconductor has marked the GAL22V10D-20LPI as obsolete. Buyers should verify date code and traceability requirements with their sourcing desk.
Package and board-fit — 24-pin DIP footprint
The 24-DIP (0.300", 7.62 mm) package with through-hole mounting is a standard 0.100-inch pitch DIP footprint. The supplier device package is 24-PDIP. This form factor is common in legacy PLD sockets and through-hole prototyping boards; no fine-pitch or BGA reflow profile is needed. The EE PLD programmable type means the configuration is stored in EEPROM cells — it retains the logic pattern when power is removed and can be reprogrammed in-system or on a programmer. No external configuration memory or boot PROM is required.