Lattice Semiconductor lists the GAL22V10D-15QJN as obsolete.
10 macrocells, 15 ns — right-sizing the glue logic
The GAL22V10D-15QJN integrates 10 macrocells in an EE PLD fabric — enough to replace a handful of 74-series logic gates or a small state machine without reaching for an SRAM-based FPGA. Maximum propagation delay (tpd) is 15 ns, which sets the ceiling for combinatorial paths through the device. At 5V nominal, this part keeps up with most 33–50 MHz bus interfaces and address decoding tasks.
5V supply, 0–75°C — commercial temperature band
Internal supply range is 4.75V to 5.25V, the classic 5V logic rail. Operating temperature is 0°C to 75°C (commercial grade), so this part suits indoor equipment, test gear, and telecom racks — not extended industrial or automotive environments. Packaged in a 28-lead PLCC (J-Lead) with an 11.51 mm × 11.51 mm body. The J-bend footprint saves board space compared to a DIP but requires a PLCC socket or a hot-air rework station for removal.