24-DIP through-hole — the board-fit story
The GAL22V10D-15LPI: The 24-PDIP supplier package matches the 24-DIP case code, so the same PCB layout serves both. No exposed thermal pad or heatsink tab — the plastic DIP body dissipates through the leads and board copper. For a 10-macrocell EE PLD drawing under 100 mA from a 5 V rail, the junction temperature stays well inside the -40 to 85°C industrial range without airflow.
What the 15 ns tpd means on the bench
The 15 ns propagation delay (tpd) is the pin-to-pin delay from any input through the sum-of-products array and macrocell to the registered or combinatorial output. For a 5 V system clocked at 33 MHz, the 15 ns tpd leaves about 15 ns of the 30 ns cycle for setup and routing — tight but workable if the board trace lengths are kept under 150 mm. This is the -15 speed grade, the middle of the GAL22V10 speed bins. The EE PLD architecture uses EEPROM cells for the logic array — no battery backup needed, and the pattern survives 100+ program/erase cycles in a typical debug session.
Obsolete — what that means for the BOM line
Lattice Semiconductor lists the GAL22V10D-15LPI as Obsolete. The part is sourced through independent distribution channels — quantities are lot-specific and confirmed at RFQ. For a board that still runs this 24-DIP GAL, the procurement path is the surplus and broker market. A board spin to a surface-mount CPLD (e.g., the ispMACH or MachXO families in TQFP) is the long-term migration, but for keeping a legacy line running, the DIP-24 GAL22V10 remains orderable through the independent channel.
5 V supply and industrial temp — legacy system fit
The -40 to 85°C industrial temperature grade covers factory-floor and outdoor cabinet environments where a commercial 0-70°C part would drift out of timing. The GAL22V10D-15LPI is an EE PLD, not a one-time programmable fuse part. The EEPROM cells can be erased and reprogrammed in-system or on a programmer — useful for field updates or for recovering a board where the pattern was lost.