What the 15 ns tpd means for your timing budget
The Lattice GAL22V10D-15LJI is a 10-macrocell EE PLD from the GAL®22V10 family, with a maximum propagation delay (tpd) of 15 ns. That 15 ns is the pin-to-pin combinatorial delay at 5 V supply — it sets the ceiling on how fast registered or combinatorial logic can propagate through the device. For a 50 MHz clock, one tpd consumes roughly three-quarters of a clock period in combinatorial paths, leaving little margin for external routing delays; this part is sized for 33 MHz and below glue logic rather than high-speed state machines.
28-PLCC footprint and board integration
Housed in a 28-lead PLCC (J-Lead) package with a body size of 11.51 x 11.51 mm, the GAL22V10D-15LJI sits in a standard JEDEC footprint. The J-Lead gull-wing variant is surface-mount, but the PLCC socket option also exists for prototyping — the same land pattern accepts either a soldered part or a low-profile socket.
Lattice Semiconductor has marked the GAL22V10D-15LJI as Obsolete. For new designs, the closest active Lattice CPLD families (such as the ispGAL22V10 or the MachXO series) offer similar macrocell counts but with different package options and supply voltages — a board spin is required.
Temperature grade and operating environment
The 15 ns tpd is specified across this full range, though propagation delay typically increases by 0.3% per °C above 25°C — budget an extra 2-3 ns at the hot end for combinatorial paths.