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Lattice Semiconductor Corporation GAL16V8Z-12QP — FPGA / CPLD & Programmable Logic

Lattice GAL16V8Z-12QP EE PLD, 12 ns, 8 macrocells, 20-DIP

MPNGAL16V8Z-12QP
Active

Lattice Semiconductor Corporation GAL® 16V8 series EE PLD, GAL16V8Z-12QP, 12 ns speed, 8 macrocells, 20-DIP through-hole, 4.75V~5.25V supply.

$3.6000Ref. price · indicative, final on quote
Packaging20-DIP (0.300", 7.62mm)
RoHSRoHS non-compliant
SeriesGAL® 16V8
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

GAL16V8Z-12QP specifications
ParameterValue
SeriesGAL® 16V8
MountingThrough Hole
Programmable typeEE PLD
Voltage - input4.75V ~ 5.25V
Speed12 ns
PackageBulk
Case20-DIP (0.300\", 7.62mm)
Number of macrocells8

Product details

12 ns speed — the timing closure ceiling

The GAL16V8Z-12QP: The 12 ns propagation delay sets the maximum combinational logic path the part can close — a signal through the device takes up to 12 ns from input to registered output, which governs the clock rate the rest of the board can run. Eight macrocells give the logic capacity for glue-logic consolidation: address decoding, state machines, or bus-interface translation in a single 20-pin DIP.

Frequently asked questions

What is the closest functional second-source to GAL16V8Z-12QP?

The GAL16V8ZD-15QP is the closest peer: same GAL® 16V8 series, same 20-DIP through-hole package, same 8 macrocells and 5 V supply, but with a 15 ns speed grade instead of 12 ns. It drops into the same socket without rewiring, though the slower propagation delay may shift timing closure in the logic path.

What is the speed rating of GAL16V8Z-12QP?

The listed propagation delay is 12 ns — the maximum time from a registered input to the output, which sets the combinational logic path timing budget for the design.