8 macrocells at 7.5 ns — the glue-logic speed floor
The GAL16V8D-7LJNI is an 8-macrocell electrically erasable PLD from Lattice's GAL16V8 series, with a 7.5 ns maximum propagation delay (tpd). That delay sets the combinatorial logic throughput ceiling — any path through the device must settle within 7.5 ns, so it fits as PAL/GAL replacement in existing 5 V backplanes where the timing budget is already allocated.
Obsolete — what that means for your BOM line
Lattice Semiconductor has marked the GAL16V8D-7LJNI as Obsolete. For existing designs already qualified on this PLD, the supply path runs through independent distribution — quantities are lot-specific and confirmed at RFQ. No second-source cross-reference is maintained.
Package and board-fit — 20-PLCC J-Lead
Housed in a 20-lead PLCC with J-bend leads (20-LCC J-Lead), the body measures 9x9 mm. The J-Lead footprint is a legacy surface-mount format — the solder joint is hidden under the package, so visual inspection requires an X-ray or angled borescope. The supplier device package is 20-PLCC (9x9). Supplied in tube packaging, not tape-and-reel — factor this into the pick-and-place feeder setup if the line is set up for embossed carrier tape.