8-macrocell EE PLD in a 20-PLCC footprint
The Lattice GAL16V8D-7LJ is an electrically erasable programmable logic device from the GAL®16V8 family, packing 8 macrocells in a 20-PLCC package with J-leads. The 20-LCC (J-Lead) package, also specified as 20-PLCC (9x9 mm), is a surface-mount square body with J-bend leads on all four sides. It is hand-solderable with a fine-tip iron and a steady hand — the 1.27 mm lead pitch gives you room to probe and rework without a microscope.
What the 7.5 ns tpd means on the bench
The 7.5 ns tpd(1) max is the propagation delay from any input through the combinatorial path to any output — the time it takes for a logic transition to appear at the pin after the input crosses the threshold. In a 5 V system clocked at 33 MHz (30 ns period), a 7.5 ns delay eats a quarter of the cycle, leaving 22.5 ns for the rest of the path. That is tight but workable for address decoding or state-machine control logic where the PLD sits between the CPU and peripherals. The EE PLD architecture means the configuration is stored in EEPROM cells — it retains the logic pattern when power is removed and can be reprogrammed in-circuit hundreds of times. No UV eraser needed, no quartz window. The 8 macrocells can be configured as registered or combinatorial outputs, with programmable polarity per pin.
Quantities are lot-specific and confirmed at RFQ. The 20-PLCC footprint is shared with other GAL16V8 speed grades (e.g., -10, -15) and with the Atmel ATF16V8 series — a pin-compatible alternative may exist, but no official cross-reference is recorded here.