Lattice Semiconductor has marked the GAL16V8D-25QPNI as Obsolete. Available for sourcing through independent distribution channels.
8 macrocells at 25 ns — timing fit for legacy glue logic
The GAL16V8D-25QPNI is an electrically erasable PLD (EE PLD) from the GAL®16V8 series, offering 8 macrocells with a maximum propagation delay (tpd) of 25 ns. This delay sets the ceiling for registered logic — a 25 ns tpd means the part supports clock frequencies up to roughly 40 MHz, making it suitable for address decoding, bus interface logic, or state machines in legacy 8/16-bit systems. The 5 V supply rail is a distinguishing constraint — newer CPLD families have moved to 1.8 V or 2.5 V cores, so this part fits only designs that still carry a 5 V plane.
Through-hole PDIP-20 — board-fit and integration
Housed in a 20-lead PDIP (0.300", 7.62 mm) package with through-hole mounting. The 0.100-inch pitch is breadboard- and prototype-friendly, and the 300-mil body width fits standard DIP sockets. No fine-pitch or BGA reflow profile needed — hand-solder or wave-solder compatible. Supplied in tube packaging. The base product number is GAL16V8; the full order code decodes the speed grade (25 ns), package (Q = PDIP), and temperature range (N = industrial, I = lead-free finish per Lattice's older suffix convention).