Lattice Semiconductor GAL®16V8 series EE PLD, GAL16V8D-25QJNI, 8 macrocells, 25 ns tpd(1) max, 20-LCC (J-Lead) surface mount, -40°C to 85°C.
| Parameter | Value |
|---|---|
| Series | GAL®16V8 |
| Mounting | Surface Mount |
| Programmable type | EE PLD |
| Voltage supply - internal | 4.5V ~ 5.5V |
| Operating temperature | -40°C~85°C(TA) |
| Package | Tube |
| Case | 20-LCC (J-Lead) |
| Number of macrocells | 8 |
| Delay time tpd(1) max | 25 ns |
The GAL16V8D-25QJNI is an 8-macrocell electrically erasable PLD from the GAL®16V8 series, in a 20-lead PLCC (J-Lead) package. The 25 ns maximum propagation delay (tpd(1)) sets the speed grade — combinatorial paths settle within 25 ns, making it suitable for glue-logic replacement and address decoding in 5 V systems where the bus timing budget allows that latency.
Any replacement must be evaluated for macrocell count, 5 V supply compatibility, and 25 ns propagation delay — a board spin or logic redesign may be required.