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Lattice Semiconductor Corporation GAL16V8D-25LPN — FPGA / CPLD & Programmable Logic

GAL16V8D-25LPN Lattice EE PLD, 8 macrocells, 25 ns, 20-PDIP

MPNGAL16V8D-25LPN
Obsolete

Lattice Semiconductor Corporation GAL®16V8 series EE PLD, 8 macrocells, 25 ns propagation delay, 4.75 V ~ 5.25 V internal supply, 0°C ~ 75°C, 20-DIP (0.300", 7.62 mm) through-hole package, tube.

$1.1000Ref. price · indicative, final on quote
Lattice Semiconductor Corporation GAL16V8D-25LPN datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

GAL16V8D-25LPN specifications
ParameterValue
SeriesGAL®16V8
MountingThrough Hole
Programmable typeEE PLD
Voltage supply - internal4.75V ~ 5.25V
Operating temperature0°C~75°C(TA)
PackageTube
Case20-DIP (0.300\", 7.62mm)
Number of macrocells8
Delay time tpd(1) max25 ns

Product details

The GAL16V8D-25LPN: For existing BOM lines or repair stock, this part is sourced through independent distribution channels.

What the 25 ns delay means for fit

The 25 ns tpd(1) sets the combinatorial-logic speed ceiling: registered outputs toggle at up to about 40 MHz, but the actual system clock depends on the external feedback path and output load capacitance. For a glue-logic replacement in a legacy 5 V bus, this delay is typical of the original GAL16V8 generation. Eight macrocells, each configurable as registered or combinatorial, cover small-scale state machines, address decoders, or bus-interface logic in a single 20-pin DIP footprint.

Frequently asked questions

What is the closest pin-compatible alternative to the GAL16V8D-25LPN?

No pin-compatible successor is listed by Lattice. The GAL®16V8 family has been superseded by newer architectures (e.g., ispGAL or GAL22V10 families), but those are not drop-in replacements — a board spin or adapter socket is required. Confirm the BOM position's logic requirements before substituting.