8 macrocells, 20 ns — field-swappable logic fix
The Lattice GAL16V8D-20QPNI is an EE PLD from the GAL®16V8 series, packing 8 macrocells with a 20 ns maximum propagation delay. Housed in a 20-pin DIP (0.300", 7.62 mm) with through-hole mounting, this part is socket-friendly — you can swap it on site with basic tools, no hot-air station needed. The tube packaging keeps leads aligned for manual insertion.
Lattice Semiconductor has marked the GAL16V8D-20QPNI as obsolete. No pin-compatible direct replacement is documented from Lattice, so verify your BOM position against the original design files before committing.
What the 20 ns tpd means for your logic
The 20 ns tpd(1) max sets the combinatorial delay from input to registered output. In a 5 V system clocked at 25 MHz, this gives about one clock period of logic — enough for simple state machines and address decoding, but tight for pipelined designs that chain multiple PAL/GAL devices. With 8 macrocells, each configurable as registered or combinatorial, this part suits glue-logic consolidation where a handful of 74-series TTL packages would otherwise occupy board space. The EE PLD technology means it retains the pattern without a battery — reprogrammable in-system if your programmer supports the 16V8 architecture.