Lattice Semiconductor has marked the GAL16V8D-15QJ as Obsolete.
8 macrocells, 15 ns tpd — right-size the glue logic
That 15 ns sets the combinatorial-logic ceiling — any path through the device must settle within that window, so it comfortably handles 33 MHz address decoding or state-machine transitions without extra wait states.
20-PLCC footprint — board-fit note
Housed in a 20-lead PLCC (J-Lead) package, the GAL16V8D-15QJ occupies a 9x9 mm body (supplier device package 20-PLCC). The J-lead footprint is common for through-hole reflow or socketed applications — verify the pad geometry matches your existing PLCC-20 land pattern before committing the BOM.