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Lattice Semiconductor Corporation GAL16V8D-15LPI — FPGA / CPLD & Programmable Logic

Lattice GAL16V8D-15LPI EE PLD, 8 macrocells, 20-PDIP

MPNGAL16V8D-15LPI
Obsolete

Lattice Semiconductor GAL®16V8 series, EE PLD, 8 macrocells, Through Hole, 20-DIP (0.300", 7.62mm), 20-PDIP, Tube.

Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

GAL16V8D-15LPI specifications
ParameterValue
SeriesGAL®16V8
MountingThrough Hole
Programmable typeEE PLD
PackageTube
Case20-DIP (0.300\", 7.62mm)
Number of macrocells8

Product details

What the 8-macrocell count means for your logic glue

The GAL16V8D-15LPI is an electrically erasable PLD from Lattice's GAL®16V8 series, packing 8 macrocells in a 20-pin DIP package. Eight macrocells cover typical address decoding, bus arbitration, or state-machine logic that would otherwise consume a handful of 74-series logic packages — one GAL replaces several SOIC-14s and cuts the board footprint. The EE PLD architecture means the device is in-system reprogrammable; the same socket can serve prototype iterations and production units without a UV eraser cycle.

Lattice Semiconductor has marked the GAL16V8D-15LPI as obsolete. For existing BOM lines or legacy board repairs, the part is sourced through independent distribution against an RFQ.

Package and board-fit — through-hole DIP for legacy or prototyping

The 20-DIP (0.300", 7.62mm) through-hole package mates with standard 0.100-inch pitch sockets or wave-solder pads. The 20-PDIP footprint is common across the GAL16V8 family, so a board laid out for one speed grade accepts the -15LPI variant without a layout change. Supplied in tube packaging — 15 or 25 per tube depending on the factory fill — suitable for manual insertion or tube-fed auto-insertion machines.

Frequently asked questions

What is the closest pin-compatible alternative to the GAL16V8D-15LPI?

No official pin-compatible successor is recorded from Lattice. Other GAL16V8 speed grades or the GAL22V10 family share the same 20-pin DIP footprint but differ in macrocell count or programming algorithm — verify timing and logic fit before substituting.