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Lattice Semiconductor Corporation GAL16V8D-15LP — FPGA / CPLD & Programmable Logic

GAL16V8D-15LP Lattice GAL16V8 EE PLD, 15 ns, 8 macrocells

MPNGAL16V8D-15LP
Obsolete

Lattice Semiconductor GAL®16V8 series EE PLD, GAL16V8D-15LP, 8 macrocells, 15 ns propagation delay, 20-DIP (0.300", 7.62mm) through-hole package, 4.75V~5.25V internal supply, 0°C~75°C operating temperature.

$1.2200Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

GAL16V8D-15LP specifications
ParameterValue
SeriesGAL®16V8
MountingThrough Hole
Programmable typeEE PLD
Voltage supply - internal4.75V ~ 5.25V
Operating temperature0°C~75°C(TA)
PackageBulk
Case20-DIP (0.300\", 7.62mm)
Number of macrocells8
Delay time tpd(1) max15 ns

Product details

Lattice Semiconductor has marked the GAL16V8D-15LP as obsolete.

8 macrocells, 15 ns propagation delay — what it means for the BOM

The GAL16V8D-15LP is an EE PLD from the GAL®16V8 series, offering 8 macrocells with a maximum propagation delay (tpd) of 15 ns. This delay sets the ceiling for registered output toggling — at 15 ns the part supports clock rates up to roughly 66 MHz in a typical glue-logic application, though the actual system speed depends on the external routing and load capacitance. The 8 macrocells each can be configured as combinational or registered outputs, making this a fit for address decoding, state machines, or bus-interface logic where a handful of PAL/GAL equations replace discrete 7400-series logic.

20-DIP through-hole — board-fit and supply rail

Housed in a 20-pin DIP (0.300", 7.62mm body width) with through-hole mounting, the GAL16V8D-15LP fits legacy PCB layouts and prototyping boards. The supplier device package is 20-PDIP. Operating temperature is specified for 0°C to 75°C, the commercial grade, so it is suited for indoor equipment and benchtop environments rather than extended-temperature industrial or automotive zones.