8-macrocell EE PLD for 5 V glue logic
The Lattice GAL16V8D-15LJ is an electrically erasable programmable logic device (EE PLD) from the GAL®16V8 family, packing 8 macrocells in a 20-PLCC surface-mount package. With a 15 ns maximum propagation delay (tpd), it fits address decoding, bus arbitration, and state-machine replacement in systems clocked up to about 66 MHz — the speed grade that matters is the tpd, not the toggle rate, because the combinatorial path through the logic array sets the timing closure ceiling.
Obsolete — independent-channel sourcing
No pin-compatible direct replacement from Lattice is documented, so a board spin may be required if migrating to a newer CPLD family.
Package and temperature grade
Housed in a 20-lead PLCC (J-Lead) with a 9x9 mm body (supplier device package 20-PLCC), the part is suited for rework-friendly surface-mount assembly — the J-lead profile allows visual inspection and hand-soldering with a standard iron. Rated for 0°C to 75°C ambient (commercial temperature range), it is not qualified for industrial or automotive environments — no AEC-Q or extended-temp variant is listed.