Skip to main content
Log in
Lattice Semiconductor Corporation GAL16V8D-10LPNI — FPGA / CPLD & Programmable Logic

Lattice GAL16V8D-10LPNI EE PLD, 8 macrocells, 10 ns, PDIP-20

MPNGAL16V8D-10LPNI
Obsolete

Lattice Semiconductor Corporation GAL®16V8 series EE PLD, GAL16V8D-10LPNI, 8 macrocells, 10 ns propagation delay, 4.5 V to 5.5 V supply, -40 to 85 °C, 20-PDIP, tube.

Lattice Semiconductor Corporation GAL16V8D-10LPNI datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

GAL16V8D-10LPNI specifications
ParameterValue
SeriesGAL®16V8
MountingThrough Hole
Programmable typeEE PLD
Voltage supply - internal4.5V ~ 5.5V
Operating temperature-40°C~85°C(TA)
PackageTube
Case20-DIP (0.300\", 7.62mm)
Number of macrocells8
Delay time tpd(1) max10 ns

Product details

8-macrocell EE PLD in a 20-pin DIP

The GAL16V8D-10LPNI is an electrically erasable PLD from Lattice's GAL®16V8 series, packing 8 macrocells in a 20-pin DIP package (0.300-inch body, 7.62 mm width). It is programmed as an EE PLD, meaning the configuration is stored in EEPROM cells and can be erased and reprogrammed in-circuit or on a programmer.

Lattice Semiconductor has marked the GAL16V8D-10LPNI as obsolete. No official successor part number is listed in the available records, so a direct pin-compatible drop-in from Lattice is not confirmed. No stock-holding claim is made; availability is verified at quote time.

The tube packaging is typical for through-hole PLDs — the tubes protect the leads during handling and are compatible with auto-insertion equipment that feeds from tube magazines.

Frequently asked questions

What is the propagation delay of the GAL16V8D-10LPNI?

The maximum propagation delay (tpd) is 10 ns. This is the combinatorial delay from input to registered output and sets the upper limit for the logic path timing in the design.