8-macrocell EE PLD for glue-logic consolidation
The Lattice GAL16V8D-10LP is an electrically erasable programmable logic device (EE PLD) from the GAL®16V8 series, packing 8 macrocells in a 20-pin DIP package. It replaces multiple 74-series TTL or 4000-series CMOS logic gates with a single reprogrammable part, reducing board area and BOM line count on legacy through-hole boards. The 10 ns maximum propagation delay (tpd) means the device can handle clock rates up to roughly 50 MHz in registered mode — fast enough for address decoding, bus arbitration, or state machines in 8-bit and 16-bit microcontroller systems. The 5 V ±5% supply rail matches the logic levels of classic 8051, 68HC11, and x86 peripheral buses.
Lattice Semiconductor has marked the GAL16V8D-10LP as obsolete. For a new design, the GAL®16V8 family has been superseded by Lattice's ispGAL and MachXO families, but those are different package and pinout — a board spin is required. If you are maintaining an existing BOM that calls out this exact DIP footprint, the surplus channel is the practical path.
20-pin DIP — board-fit for legacy sockets
The 20-DIP (0.300-inch row spacing, 7.62 mm body width) and through-hole mounting target boards that still use socketed PLDs. The 0°C to 75°C commercial temperature range limits deployment to indoor, non-condensing environments — not suitable for automotive or extended industrial temperature zones without qualification testing. The EE PLD technology supports in-system reprogramming through a standard 5 V programming algorithm, but the DIP package requires removal from the socket for reprogramming unless the board provides a programming header. Plan for socketed programming during manufacturing or use a pre-programmed device from a programming house.