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Intel EPM570ZM256I8N — FPGA / CPLD & Programmable Logic

EPM570ZM256I8N MAX II CPLD, 440 Macrocells, 9 ns, 160 I/O

MPNEPM570ZM256I8N
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Altera MAX® II CPLD, EPM570ZM256I8N, 570 logic elements, 440 macrocells, 9 ns tpd, 160 I/O, 1.71V–1.89V core, -40°C to 100°C, 256-TFBGA tray.

$26.0000Ref. price · indicative, final on quote
Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

EPM570ZM256I8N specifications
ParameterValue
SeriesMAX® II
MountingSurface Mount
Programmable typeIn System Programmable
Voltage supply - internal1.71V ~ 1.89V
Operating temperature-40°C~100°C(TJ)
PackageTray
Number of i (O)160
Case256-TFBGA
Number of macrocells440
Delay time tpd(1) max9 ns
Number of logic elements (Blocks)570

Product details

MAX II CPLD — 570 logic elements in a 256-ball BGA

The Altera EPM570ZM256I8N is a MAX II family CPLD packing 570 logic elements and 440 macrocells in a 256-ball MBGA (11x11 mm) footprint. It delivers 160 user I/O with a 9 ns pin-to-pin propagation delay, running on a 1.71 V to 1.89 V core supply. In-system programmability via JTAG means you can update the glue logic without pulling the board — useful for field revisions or multi-configuration boot sequences.

9 ns tpd — what it buys on the bus

The 9 ns propagation delay is the combinatorial path from any input to any output through one macrocell.

Frequently asked questions

Is EPM570ZM256I8N compatible with 3.3V I/O?

Yes. The I/O banks are powered separately from the core. By connecting the VCCIO pins to 3.3 V, the I/O pads will drive and receive 3.3 V logic levels. Each of the four banks can run a different VCCIO voltage, so mixed 1.8 V / 2.5 V / 3.3 V interfaces are possible on the same device.