440 macrocells at 5.4 ns — the logic-density fit
The Intel EPM570T144C5 is a MAX II CPLD packing 440 macrocells with a 5.4 ns maximum pin-to-pin propagation delay (tpd1). That delay is the combinatorial path from any input through the logic array to any output — for a 50 MHz bus bridge, the 5.4 ns ceiling leaves about 14 ns of the 20 ns cycle for external setup and hold after the CPLD's own delay is consumed. The 570 logic elements back the macrocell count with fine-grain routing, so a 16-bit address decoder plus a 4-state sequencer fits without splitting across multiple devices.
144-LQFP with 116 user I/O — board integration
The 0.5 mm pitch demands a 4-layer PCB for reliable fan-out on the inner rows — two-layer boards will struggle with escape routing on the full I/O count.
Dual supply and in-system programming
In-system programmable via the JTAG interface (IEEE 1149.1), the device is configured on the board without a socket or external programmer; the 4-pin JTAG header consumes four of the 116 I/O unless boundary-scan is used. Programming is supported in Quartus Prime — the device ID is recognized by the software's device list for the MAX II family.