MAX II CPLD — 570 logic elements in a 100-TQFP
The Intel EPM570T100C5 is a MAX II family CPLD with 570 logic elements and 440 macrocells, housed in a 100-TQFP (14x14 mm) surface-mount package. It delivers 76 user I/O and a 5.4 ns maximum pin-to-pin delay (tpd1).
5.4 ns pin-to-pin delay — timing margin for combinatorial paths
The 5.4 ns tpd1 maximum means combinatorial signals propagate from any input pin through the logic array to any output pin within that window.
Intel lists the EPM570T100C5 as Active. No last-time-buy notice, no obsolescence date.
