440-macrocell CPLD in a 100-TQFP
The Intel EPM570T100C3 is a MAX® II family CPLD packing 440 macrocells and 570 logic elements in a 100-TQFP (14x14 mm) footprint — enough logic for glue-logic consolidation, address decoding, or state-machine control in a board area that fits under a 0.50 mm pitch MCU. With 76 user I/O and a propagation delay (tpd1) of 5.4 ns max, it handles 100+ MHz bus interfaces without adding a wait state on a 10 ns memory access.
In-system programmable, active lifecycle
The device is in-system programmable (ISP) via JTAG — no socket or UV eraser needed; the non-volatile configuration holds on power-down.
