The Altera EPM570GT144C3N is a MAX® II family CPLD with 570 logic elements and 440 macrocells in a 144-LQFP package. It is in-system programmable via JTAG, runs on a 1.71 V–1.89 V core supply, and delivers a propagation delay of 5.4 ns. With 116 user I/O, it handles board-level glue logic, address decoding, and control sequencing in industrial and commercial equipment operating from 0°C to 85°C.
5.4 ns tpd — the timing number that matters
The 5.4 ns pin-to-pin delay (tpd1) sets the maximum combinational path this CPLD can close.
440 macrocells and 116 I/O — logic density and pinout
The 440 macrocells and 116 I/O come on a 144-LQFP package.
