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Intel EPM570GT100C5 — FPGA / CPLD & Programmable Logic

Intel EPM570GT100C5 CPLD, MAX II, 570 LE, 5.4 ns

MPNEPM570GT100C5
Active

Intel MAX® II series CPLD, EPM570GT100C5, 570 logic elements, 440 macrocells, 5.4 ns pin-to-pin delay, 76 I/O, 100-TQFP (14x14 mm), 1.71V–1.89V core, 0°C to 85°C, in-system programmable.

$69.0000Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

EPM570GT100C5 specifications
ParameterValue
SeriesMAX® II
MountingSurface Mount
Programmable typeIn System Programmable
Voltage supply - internal1.71V ~ 1.89V
Operating temperature0°C~85°C(TJ)
PackageTray
Number of i (O)76
Case100-TQFP
Number of macrocells440
Delay time tpd(1) max5.4 ns
Number of logic elements (Blocks)570

Product details

MAX II CPLD — 570 LEs, 5.4 ns, 76 I/O

The Intel EPM570GT100C5 is a MAX® II family CPLD delivering 570 logic elements and 440 macrocells in a 100-TQFP (14x14 mm) package. Pin-to-pin propagation delay (tpd1) maxes at 5.4 ns, making it a fit for address decoding, bus bridging, and state-machine glue logic where combinatorial speed matters. The 76 user I/O give enough headroom for a moderate-density interface without stepping up to a larger package. Core supply is 1.71 V to 1.89 V, with in-system programmability via JTAG — no external programmer voltage needed. Operating temperature covers 0°C to 85°C, suited for commercial and industrial indoor environments.

Frequently asked questions

What is the difference between EPM570GT100C5 and EPM570T100C5?

The 'G' in EPM570GT100C5 indicates a specific ordering code variant within the MAX II family — typically a lead-free or RoHS-compliant finish. The EPM570T100C5 is a non-'G' variant; the core logic (570 LEs, 440 macrocells, 5.4 ns) is identical. Confirm the exact finish requirement with your BOM before substituting.

Where can I buy EPM570GT100C5?

This part is sourced and quoted to order through independent distribution. Submit an RFQ for current pricing and availability — lead time and stock position are confirmed at quote time.

How to program the Intel EPM570GT100C5?

The EPM570GT100C5 is in-system programmable via the JTAG interface (IEEE 1149.1). Intel's Quartus II software (or later) generates the programming file; a standard USB-Blaster or compatible JTAG cable connects to the TMS, TCK, TDI, TDO pins. No external VPP supply is needed — the core voltage supplies the programming logic.