MAX II CPLD with 440 macrocells and 5.4 ns pin-to-pin delay
The Intel EPM570GM256C5N is a MAX® II complex programmable logic device (CPLD) with 570 logic elements and 440 macrocells, packaged in a 256-ball TFBGA (11x11 mm). It delivers a 5.4 ns propagation delay (tpd1) and supports 160 user I/O, making it suitable for glue-logic consolidation, address decoding, and control-path sequencing in telecom infrastructure, industrial controllers, and test equipment.
5.4 ns tpd — timing margin for the bus
The 5.4 ns pin-to-pin delay (tpd1) is the combinatorial path through a single macrocell.
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