440-macrocell CPLD for board-level glue logic
The Intel EPM570F256C4 is a MAX® II CPLD with 440 macrocells and 570 logic elements, housed in a 256-ball FBGA (17x17 mm) package. It delivers 160 user I/O and a 5.4 ns pin-to-pin propagation delay.
5.4 ns tpd — timing margin for the bus
The 5.4 ns combinatorial delay (tpd1) sets the window for signal propagation through a single LUT path. The smaller EPM240F100C5N runs 4.7 ns tpd but only offers 192 macrocells and 80 I/O.
No last-time-buy window or NRND flag is in effect.
