The Intel EPM570F100I5N is a MAX® II family CPLD packing 570 logic elements and 440 macrocells in a 100-ball FBGA (11x11 mm) footprint. It gives you 76 user I/O with a 5.4 ns pin-to-pin delay — fast enough for address decoding, bus bridging, or state-machine glue in an industrial controller or telecom line card. The -40°C to 100°C junction temperature range puts it on the factory floor or inside an outdoor enclosure without derating drama.
5.4 ns tpd — what it buys you
The 5.4 ns propagation delay suits address decoding or bus bridging. The EPM240F100C5N sibling runs at 4.7 ns but has 192 macrocells versus 440.
Dual-voltage supply — no level shifter needed
Tie VCCIO to the rail your downstream logic runs on.