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Intel EPM570F100C4N — FPGA / CPLD & Programmable Logic

Intel EPM570F100C4N MAX II CPLD, 440 macrocells, 5.4ns

MPNEPM570F100C4N
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Intel MAX® II CPLD, EPM570F100C4N, 440 macrocells, 570 logic elements, 76 I/O, 5.4 ns tpd, 100-FBGA (11x11), tray, 2.5V/3.3V internal, 0°C to 85°C.

$8.0000Ref. price · indicative, final on quote
Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

EPM570F100C4N specifications
ParameterValue
SeriesMAX® II
MountingSurface Mount
Programmable typeIn System Programmable
Voltage supply - internal2.5V, 3.3V
Operating temperature0°C~85°C(TJ)
PackageTray
Number of i (O)76
Case100-LBGA
Number of macrocells440
Delay time tpd(1) max5.4 ns
Number of logic elements (Blocks)570

Product details

MAX II CPLD — 440 macrocells in 100-ball FBGA

The Intel EPM570F100C4N is a MAX® II CPLD with 440 macrocells and 570 logic elements in a 100-ball FineLine BGA (11x11 mm) package — the mid-density member of the MAX II family, positioned between the 240-macrocell EPM240 and the 570-macrocell EPM570. It delivers 76 user I/O, a 5.4 ns pin-to-pin propagation delay (tpd1), and is in-system programmable via JTAG.

What 440 macrocells and 5.4 ns tpd mean for your BOM

440 macrocells translates to roughly 440 flip-flops or combinatorial logic blocks — enough for glue logic, address decoding, state machines, or a small bus bridge. The 5.4 ns tpd(1) maximum means a signal from a registered input to a combinatorial output settles within 5.4 ns, so the CPLD can sit between a 100 MHz bus and a slower peripheral without adding a full clock cycle of delay. 76 I/O in a 100-ball BGA leaves 24 balls for power, ground, and dedicated function pins — a good ratio for a 0.8 mm pitch array. The 11x11 mm body fits on a 4-layer board with two signal layers; fan-out under the BGA is manageable with 0.30 mm vias.

This dual-supply flexibility lets the CPLD bridge a 3.3 V peripheral bus to a 2.5 V core logic plane without an external level shifter. Operating temperature is 0°C to 85°C (TJ), the commercial range — not rated for -40°C cold start.

Frequently asked questions

What is the replacement for EPM570F100C4N?

If you need a higher-density MAX II, the EPM570F100C5N is the same silicon with a faster speed grade (5.4 ns vs 4.5 ns typical). For a different package or I/O count, the EPM570T100C4N in TQFP is a pin-compatible alternative.

Does EPM570F100C4N support JTAG programming?

Yes — the EPM570F100C4N is In System Programmable through the standard JTAG interface (TDI, TDO, TMS, TCK). The MAX II family uses the IEEE 1532 extension of JTAG for in-system configuration, and the 100-ball BGA routes the JTAG pins to dedicated balls.

What is the difference between EPM570F100C4N and EPM570F100C5N?

The -C4N suffix indicates the standard speed grade with a 5.4 ns tpd(1) maximum propagation delay, while the -C5N is a faster speed grade typically rated at 4.5 ns tpd. Both have the same 440 macrocells, 76 I/O, and 100-ball FBGA package. The -C5N is the higher-performance variant for timing-critical paths.