Intel MAX® II CPLD, EPM1270T144C4N, 980 macrocells, 1270 logic elements, 116 I/O, 6.2 ns tpd(1) max, 144-LQFP, 2.5V/3.3V internal supply, 0°C to 85°C operating temperature, in-system programmable.
| Parameter | Value |
|---|---|
| Series | MAX® II |
| Mounting | Surface Mount |
| Programmable type | In System Programmable |
| Voltage supply - internal | 2.5V, 3.3V |
| Operating temperature | 0°C~85°C(TJ) |
| Package | Tray |
| Number of i (O) | 116 |
| Case | 144-LQFP |
| Number of macrocells | 980 |
| Delay time tpd(1) max | 6.2 ns |
| Number of logic elements (Blocks) | 1270 |
The Intel EPM1270T144C4N is a MAX II CPLD with 980 macrocells and 1270 logic elements in a 144-LQFP package. It is in-system programmable, runs on a 2.5 V or 3.3 V internal supply, and operates from 0 °C to 85 °C.
The 6.2 ns pin-to-pin delay sets the timing budget for address decoding or chip-select generation. The EPM240F100C5N runs at 4.7 ns tpd with 192 macrocells and 80 I/O.
The C4N and C5N differ in speed grade: the C4N has a 6.2 ns tpd max, while the C5N is a slower speed bin. All other ratings — 980 macrocells, 116 I/O, 144-LQFP package, 2.5V/3.3V supply — are identical. The C4N is the faster variant.
There is no direct pin-compatible second source from another manufacturer. Within the MAX II family, the EPM1270T144C5N is the same silicon at a slower speed grade. For new designs, Intel recommends migrating to a current MAX 10 or MAX V device.
The datasheet covers the MAX II family architecture, including the EPM1270T144C4N. It details the 980-macrocell array, 6.2 ns tpd timing, 116 I/O pinout, and 2.5V/3.3V supply operation. The document is available from Intel's website or through the distributor upon request.
The 144-LQFP pinout assigns 116 general-purpose I/O pins plus dedicated JTAG, clock, and supply pins. The exact pin mapping is in the MAX II family datasheet — confirm against your PCB layout before ordering, as the 0.5 mm pitch leaves no room for rework errors.