Intel MAX II CPLD, EPM1270GF256C5N, 980 macrocells, 1270 logic elements, 212 I/O, 6.2 ns pin-to-pin delay, 1.71V–1.89V core supply, 0°C–85°C operating temperature, 256-FBGA package, Tray.
| Parameter | Value |
|---|---|
| Series | MAX® II |
| Mounting | Surface Mount |
| Programmable type | In System Programmable |
| Voltage supply - internal | 1.71V ~ 1.89V |
| Operating temperature | 0°C~85°C(TJ) |
| Package | Tray |
| Number of i (O) | 212 |
| Case | 256-BGA |
| Number of macrocells | 980 |
| Delay time tpd(1) max | 6.2 ns |
| Number of logic elements (Blocks) | 1270 |
6.2 ns tpd1 is the propagation delay from input to output. For a bus decoder or address mux, this keeps glue logic out of the critical path.
Flagged eol_hot — end-of-life with last-time-buy windows active or closing. Production status is Active, but the LTB period is in effect. Source through independent distribution against an RFQ.
Yes, it is flagged end-of-life (eol_hot). Intel's MAX II family is being phased out. The product status is still listed as Active, but the LTB window is active. Source through independent distribution against an RFQ.
The suffix 'G' in EPM1270GF256C5N indicates a lead-free (RoHS-compliant) finish. The EPM1270F256C5N variant uses a standard tin-lead (SnPb) ball finish. Both are 256-FBGA, 980 macrocells, 212 I/O, 6.2 ns. The RoHS variant is the one to specify for lead-free assembly lines.
Core voltage is 1.71V–1.89V. I/O banks are configurable for 1.8V, 2.5V, or 3.3V depending on VCCIO connections.