The Altera EPM1270GF256C4N is a MAX® II family CPLD with 980 macrocells and 212 I/O in a 256-BGA package. It is in-system programmable and operates from a 1.71 V to 1.89 V core supply. The 6.2 ns pin-to-pin propagation delay (tpd) is the timing spec that matters for board-level glue logic — it sets the window for address decoding, chip-select generation, and bus-interface latching. The 212 I/O count and 1270 logic-element density place it in the mid-range of the MAX II line, suited for designs that outgrow smaller CPLDs but don't need a full FPGA.
The 6.2 ns tpd is the maximum combinatorial delay from any input to any output through a single logic level. A faster sibling like the EPM240F100C5N offers 4.7 ns tpd but only 80 I/O and 192 macrocells.
The EPM1270GF256C4N is in an end-of-life (eol_hot) lifecycle stage.
