Intel MAX® II CPLD, EPM1270F256C3, 980 macrocells, 212 I/O, 6.2 ns tpd, 2.5V/3.3V supply, 256-FBGA (17x17 mm), 0°C to 85°C, In System Programmable.
| Parameter | Value |
|---|---|
| Series | MAX® II |
| Mounting | Surface Mount |
| Programmable type | In System Programmable |
| Voltage supply - internal | 2.5V, 3.3V |
| Operating temperature | 0°C ~ 85°C (TJ) |
| Package | Tray |
| Number of i (O) | 212 |
| Case | 256-BGA |
| Number of macrocells | 980 |
| Delay time tpd(1) max | 6.2 ns |
| Number of logic elements (Blocks) | 1270 |
980 macrocells places this part in the mid-density tier of the MAX II family. The 6.2 ns tpd is fast enough for combinatorial paths; the smaller EPM240F100C5N offers 4.7 ns but only 192 macrocells and 80 I/O.
The EPM1270F256C3 is flagged as end-of-life (eol_hot). No direct pin-compatible replacement is listed in the MAX II family.
The EPM1270F256C3 and EPM1270F256C4 share the same 980-macrocell density and 256-FBGA package, but the C4 variant typically has a different speed grade (faster tpd) or temperature range. The exact difference is in the ordering code suffix — C3 is the standard speed/temperature grade.
The EPM1270F256C3 comes in a 256-ball Fine-Pitch Ball Grid Array (FBGA) package measuring 17x17 mm. The pinout is defined in the MAX II device family datasheet; the 212 I/O are arranged around the periphery with power and ground in the core.
The EPM1270F256C3 requires a 2.5V internal core supply and 3.3V I/O supply. Both rails must be present for proper operation.
The EPM1270F256C3 is In System Programmable (ISP) via a standard JTAG interface (IEEE 1149.1). Intel Quartus Prime software generates the programming file; a USB-Blaster or similar JTAG programmer connects to the TMS, TCK, TDI, TDO pins.